(1) Field of the Invention
The present invention relates to an apparatus of digitally recording and reproducing video signals in which video signals are subjected to a bit reduction coding operation so as to be recorded and reproduced, and more particularly relates to an apparatus of digitally recording and reproducing video signals in which a correction processing means is provided which is able to effectively inhibit deterioration of image quality during reproducing at a varied speed such as in a high-speed search mode.
(2) Description of the Prior Art
An apparatus for recording and reproducing video signals using a bit reduction coding technique, typically represented by a digital VTR, is composed as shown in FIG. 1. First, the structure of the apparatus will be briefly described with reference to FIG. 1. An example of the technology of this kind can be found in, for example, EP559,467. Generally, in such a digital VTR, image blocks each having a specified size are rearranged (in a block shuffling circuit 101) and the resulting blocks are subjected to a bit reduction coding operation (in a bit reduction coding circuit 102) in order to reduce information quantity to be recorded on the recording tape. Thereafter, the bit reduction coded data is added with an error correcting code (parity) (in an error correcting/coding circuit 103). Next, the resulting data is added with a synchronization signal and an ID signal for recording and reproducing (in a Sync and ID adding circuit 104). Subsequently, the thus processed data is modulated (in a modulating circuit 105) in such a manner as to inhibit the DC component thereof and recorded on a tape (a recording medium 106).
On the side for reproducing, data on the tape is demodulated (in a demodulating circuit 107). The resulting data is subjected to an error correcting operation and decoded by each coded block as a unit (in an error correcting/decoding circuit 109). During the correction in the correcting circuit, any part which could not be corrected is supplied without being decoded to a decoding/modifying circuit 110 to be modified therein.
Thereafter, the blocks are rearranged (in a block deshuffling circuit 111) in a reverse order to that executed in the recording side whereby the original video signal is reproduced.
These are the basic structure of the digital VTR using the bit reduction coding technique.
Meanwhile, there is a certain limitation in reducing information quantity by the bit reduction coding when a high-quality image must be produced. Accordingly, if the data quantity after coding is large, the data is required to be divided and recorded in many tracks taking into consideration the recording rate.
In this case, if the number of tracks divided is markedly large, the number of blocks capable of being reproduced continuously on the image frame in a high-speed playback mode becomes less, so that many block boundaries appear in rectangular regions, resulting in a deficient picture.